Typical applications of memory products require a steady miniaturization of the memory cells. A reduction of the area that is required by an individual memory cell can be obtained by shrinking the cell structure or by an increase of the number of bits that can be stored within one memory cell transistor structure. A further scaling down of the cell structures is limited by the production methods, not all of which can be modified without difficulties in order to enable the production of devices comprising the desired extremely small dimensions. This is especially true with respect to the formation of junctions between thin n-doped regions and p-doped regions. This is due to the fact that the doping atoms diffuse out of the implantation region so that the junctions become less precisely defined and the required minimal concentration of doping atoms is no longer present in the whole implantation region. This means that it becomes increasingly difficult to produce doped source/drain regions of the cell transistors and connecting buried bitlines which are sufficiently shallow.
This problem can at least partly be obviated by the use of special bitline formation masks or by an implantation that is performed self-aligned to the wordlines. In this way, the implantations can properly be adjusted and the junctions of the source and drain regions rendered more precisely limited. But this also implies that the production equipment must meet additional requirements.
Non-volatile memory cells that are electrically programmable and erasable and are especially suitable to be arranged in a virtual ground NOR architecture can be realized as charge-trapping memory cells. These cells comprise a memory layer sequence of dielectric materials with a memory layer between confinement layers of dielectric material having a larger energy band gap than the memory layer. The memory layer sequence is arranged between a channel region within a semiconductor body and a gate electrode provided to control the channel by means of an applied electric voltage. Charge carriers running from source to a drain through the channel region are accelerated and gain enough energy to be able to penetrate the lower confinement layer and to be trapped within the memory layer. The trapped charge carriers change the threshold voltage of the cell transistor structure. Different programming states can be read by applying the appropriate reading voltages.
Examples of charge-trapping memory cells are the SONOS memory cells, in which each confinement layer is an oxide and the memory layer is a nitride of the semiconductor material, usually silicon. Charge-trapping memory cells are usually programmed by channel hot electrons (CHE) and can be erased by the injection of hot holes from the channel region or by Fowler-Nordheim tunneling.
A publication by B. Eitan et al., “NROM: a Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” in IEEE Electron Device Letters, volume 21, pages 543 to 545 (2000), which is incorporated herein by reference, describes a charge-trapping memory cell with a memory layer sequence of oxide, nitride and oxide which is especially adapted to be operated with a reading voltage that is reverse to the programming voltage (reverse read). The oxide-nitride-oxide layer sequence is especially designed to avoid the direct tunneling regime and to guarantee the vertical retention of the trapped charge carriers. The oxide layers are specified to have a thickness of more than 5 nm.
The memory layer can be substituted with another dielectric material, provided the energy band gap is smaller than the energy band gap of the confinement layers. The difference in the energy band gaps should be as great as possible to secure a good charge carrier confinement and thus a good data retention. When using silicon dioxide as confinement layers, the memory layer may be tantalum oxide, cadmium silicate, titanium oxide, zirconium oxide or aluminium oxide. Also intrinsically conducting (non-doped) silicon may be used as the material of the memory layer.